Figure 12 from Air spacer for 10nm FinFET CMOS and beyond

Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node - ScienceDirect

10 nm FinFET device demonstration of a 12 % reduction of effective

Micromachines, Free Full-Text

Siliconica Just another Solid State Technology Sites site

Effect of air spacer on analog performance of underlap tri-gate FinFET - ScienceDirect

Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit

Figure 4 from FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

DTCO flow for air spacer generation and its impact on power and

November, 2016

Nanomaterials, Free Full-Text

Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era - ScienceDirect

Typical STEM of 2a) Front End of Line Air Spacer Formation in 10

November, 2016

PDF) Improved Air Spacer for Highly Scaled CMOS Technology